Tejeswini Jayakumar
About
Embedded Systems Engineer with expertise in TinyML, FPGA system design, and multimodal sensor fusion. Proven experience at CERN and in OST master projects delivering high-performance firmware and anomaly-detection pipelines. Proficient in C/C++, VHDL, and Python, with a focus on translating complex hardware constraints into validated, scalable solutions. Excels in high-stakes, collaborative environments requiring rigorous testing and system optimization.
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Skills
C Programming
Embedded
FPGA
Microcontrollers
Python
VHDL
Open for
fulltime
thesis
parttime
internship
Work Experience
CERN
2023-10 - 2024-06
FPGA Firmware Engineer
Geneva
fulltime
Performed detailed synchronization and timing analysis to interface MicroBlaze with a custom IP, ensuring 40 MHz output compatibility (VHDL and C). • Spearheaded a comparative analysis of architectural approaches on Kintex-7 FPGA, focusing on system efficiency, scalability, and determinism. Insights from this analysis were crucial in finalizing the deployment architecture. • Utilized and mastered technical tools, including Vivado for design and simulation, and Vitis for system programming. Demonstrated advanced skills in FPGA programming and system optimization. • Experimented with FreeRTOS for hard real-time implementation.
Academic Experience
OST - Ostschweizer Fachhochschule Rapperswil -
2024.09 - 2027.02
Master of Engineering, MEng in Electrical Engineering
University of Basel -
2021.09 - 2023.09
Master of Science, MSc in Biomedical Engineering